BEGIN:VCALENDAR VERSION:2.0 PRODID:DPCALENDAR CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Amsterdam BEGIN:STANDARD DTSTART:20251026T010000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:STANDARD DTSTART:20261025T010000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:DAYLIGHT DTSTART:20260329T010000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST END:DAYLIGHT END:VTIMEZONE X-WR-TIMEZONE:Europe/Amsterdam BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240521T110000 DTEND;TZID=Europe/Amsterdam:20240521T123000 UID:5891564F-975A-44BF-96BD-08E19184B825 SUMMARY:Industrial Session 1 CREATED:20240312T155037Z DTSTAMP:20240312T155037Z URL:https://ets24.nl/index.php/home/program/conference-program/industrial-session-1 DESCRIPTION:\N \N \N Moderator:\N \N Paolo Bernardi\N \N\N\N \N \N Affiliation:\N \N Politecnico di Torino (IT)\N \N\N\N \N \N A SystemC-AMS Development Framework for High Power IC Test-Hardware\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Davide Turossi, Andrea Baschirotto\N \N \N \N \N \N Affiliation:\N \N University of Milan-Bicocca (IT)\N \N \N \N \N \N Abstract:\N \N \N \N \N This paper presents a methodology based on SystemC-AMS and supported by the COSIDE graphical design environment for the development of automatic test-solutions for Integrated Circuits, which optimises the design of test-hardware and the coding of test-programs. The proposed development framework allows efficient design of test-hardware and rapid mixed-signal simulation of test-program sections, offering insight on the analog behaviour of the test-setup and on the interaction between the test-hardware, the Automatic Test Equipment and the Device Under Test, allowing early investigation and troubleshooting of the test-solution. The framework is validated within an industrial test-scenario by investigating solutions for the measurement of a rapidly changing voltage curve and by designing a narrow current pulse generator circuit where active components are used to modulate the native Automatic Test Equipment capabilities. The investigated solutions are integrated in the physical test-board and probe-card of the specific Device Under Test, and bench measurements are performed within the test-program execution.\NThe comparison between simulation results and bench measurements highlights the capability of the presented SystemC-AMS framework in offering an accurate analog representation of the modelled components and properly supporting the development of automatic test-solutions.\N \N \N \N \N \N Biography:\N \N \N \N \N My name is Davide Turossi, I am a Physics PhD student at the University of Milano-Bicocca, where I graduated in 2022. \NMy master's studies and thesis were mainly focused on semiconductors theory and electronic circuit design. \NSince 2023 I have been conducting my PhD research on automatic test development, in collaboration with Infineon Technologies, where I cooperate with the automatic testing team.\N \N \N \N \N \N Use UVM for AMS DFT through IEEE 1687 Procedural Description Language\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Geert Seuren\N \N 1\N \N , Hitu Sharma\N \N 2\N \N , Rahul Lodwal\N \N 2\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N NXP Semicoductors (NL),\N \N 2\N \N NXP Semicoductors (IN)\N \N \N \N \N \N Abstract:\N \N \N \N \N Time to market and bug free chip has put lot of pressure on the verification domain and resulted into multiple\Nverification techniques that complement each other. UVM is a reusable and robust verification environment. AMS verification tests cases can be seamlessly integrated in UVM and design module description at random abstraction level that allows effective verification test setup. In this paper we have addressed two major industrial challenges for AMS DFT Verification engineer. First is extension of IEEE 1687 to support Analog logic\Nand second is development of uniform verification platform for AMS DFT and Digital verification engineers. We have developed a methodology with which verification engineer can effectively reuse DFT test cases described in the IEEE 1687 Procedural Description Language (PDL). PDL is suited to describe the digital setup of an AMS test and written at IP level. It does guarantee a path to any production test system therefore it is able to describe the AMS test cases as an input for DFT Verification. The approach has the potential to improve the quality of DFT test cases and shall improve the overall functional test coverage of the AMS design.\N \N \N \N \N \N Biography:\N \N \N \N \N Geert got his bachelor’s degree in physics in 1988 and has been working in analog and mixed-signal testing domain in NXP for 35 years. First as mixed signal test engineer developing AMS test methods and worked on AMS DFT hardware standardization and tooling. Later joined several NXP product development groups as an AMS DfT Architect. Now working in CTO supporting NXP Business lines with AMS DfT related work and looking into improving NXP’s AMS test development flow based on IEEE1687 standard.\N \N \N \N \N \N A Comprehensive Study on Improving Probe Card Transmission Lines for Effective High-Frequency Wafer-Level Testing\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Riccardo Vettori, Alessia Galli, Ivan Giudiceandrea\N \N \N \N \N \N Affiliation:\N \N Technoprobe (IT)\N \N \N \N \N \N Abstract:\N \N \N \N \N Semiconductor manufacturers face a critical challenge in testing RF electronic devices on silicon wafers. The study emphasizes the complexities of establishing a low-loss and controlled impedance transmission line using the Probe Card interface. The pathway from the probe tip to the testing instrument includes numerous interconnecting elements, that require an enhancement to meet the demanding performance standards necessary for RF testing. This paper explores alternative approaches, eliminating the RF traces on Printed Circuit Boards (PCBs) and testing a new innovative probe type called Ultra-Phantom. Experimental results are presented, demonstrating the advantages of the architectural options under consideration.\N \N \N \N \N \N Biography:\N \N \N \N \N Alessia Galli received the Master Degree in Theoretical Physics from the Milano-Bicocca University in 2022. She has been working for Technoprobe from 2022, investigating new probing solution for RF testing. Her main research interests are focused on RF and Cryogenic wafer-level testing, expecially in the field of new Physics developements.\N \N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderator: Paolo Bernardi

Affiliation: Politecnico di Torino (IT)

A SystemC-AMS Development Framework for High Power IC Test-Hardware

Authors: Davide Turossi, Andrea Baschirotto

Affiliation: University of Milan-Bicocca (IT)

This paper presents a methodology based on SystemC-AMS and supported by the COSIDE graphical design environment for the development of automatic test-solutions for Integrated Circuits, which optimises the design of test-hardware and the coding of test-programs. The proposed development framework allows efficient design of test-hardware and rapid mixed-signal simulation of test-program sections, offering insight on the analog behaviour of the test-setup and on the interaction between the test-hardware, the Automatic Test Equipment and the Device Under Test, allowing early investigation and troubleshooting of the test-solution. The framework is validated within an industrial test-scenario by investigating solutions for the measurement of a rapidly changing voltage curve and by designing a narrow current pulse generator circuit where active components are used to modulate the native Automatic Test Equipment capabilities. The investigated solutions are integrated in the physical test-board and probe-card of the specific Device Under Test, and bench measurements are performed within the test-program execution.The comparison between simulation results and bench measurements highlights the capability of the presented SystemC-AMS framework in offering an accurate analog representation of the modelled components and properly supporting the development of automatic test-solutions.

My name is Davide Turossi, I am a Physics PhD student at the University of Milano-Bicocca, where I graduated in 2022. My master's studies and thesis were mainly focused on semiconductors theory and electronic circuit design. Since 2023 I have been conducting my PhD research on automatic test development, in collaboration with Infineon Technologies, where I cooperate with the automatic testing team.

Use UVM for AMS DFT through IEEE 1687 Procedural Description Language

Authors: Geert Seuren 1 , Hitu Sharma 2 , Rahul Lodwal 2

Affiliations: 1 NXP Semicoductors (NL), 2 NXP Semicoductors (IN)

Time to market and bug free chip has put lot of pressure on the verification domain and resulted into multipleverification techniques that complement each other. UVM is a reusable and robust verification environment. AMS verification tests cases can be seamlessly integrated in UVM and design module description at random abstraction level that allows effective verification test setup. In this paper we have addressed two major industrial challenges for AMS DFT Verification engineer. First is extension of IEEE 1687 to support Analog logicand second is development of uniform verification platform for AMS DFT and Digital verification engineers. We have developed a methodology with which verification engineer can effectively reuse DFT test cases described in the IEEE 1687 Procedural Description Language (PDL). PDL is suited to describe the digital setup of an AMS test and written at IP level. It does guarantee a path to any production test system therefore it is able to describe the AMS test cases as an input for DFT Verification. The approach has the potential to improve the quality of DFT test cases and shall improve the overall functional test coverage of the AMS design.

Geert got his bachelor’s degree in physics in 1988 and has been working in analog and mixed-signal testing domain in NXP for 35 years. First as mixed signal test engineer developing AMS test methods and worked on AMS DFT hardware standardization and tooling. Later joined several NXP product development groups as an AMS DfT Architect. Now working in CTO supporting NXP Business lines with AMS DfT related work and looking into improving NXP’s AMS test development flow based on IEEE1687 standard.

A Comprehensive Study on Improving Probe Card Transmission Lines for Effective High-Frequency Wafer-Level Testing

Authors: Riccardo Vettori, Alessia Galli, Ivan Giudiceandrea

Affiliation: Technoprobe (IT)

Semiconductor manufacturers face a critical challenge in testing RF electronic devices on silicon wafers. The study emphasizes the complexities of establishing a low-loss and controlled impedance transmission line using the Probe Card interface. The pathway from the probe tip to the testing instrument includes numerous interconnecting elements, that require an enhancement to meet the demanding performance standards necessary for RF testing. This paper explores alternative approaches, eliminating the RF traces on Printed Circuit Boards (PCBs) and testing a new innovative probe type called Ultra-Phantom. Experimental results are presented, demonstrating the advantages of the architectural options under consideration.

Alessia Galli received the Master Degree in Theoretical Physics from the Milano-Bicocca University in 2022. She has been working for Technoprobe from 2022, investigating new probing solution for RF testing. Her main research interests are focused on RF and Cryogenic wafer-level testing, expecially in the field of new Physics developements.

LAST-MODIFIED:20240521T091158Z SEQUENCE:6024081 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Van Gogh + Monet X-ACCESS:1 X-HITS:786 X-COLOR:88b3cd X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240521T161500 DTEND;TZID=Europe/Amsterdam:20240521T174500 UID:65A4C3EE-07CF-43BA-9789-8DA53E7F33FF SUMMARY:Industrial Session 2 CREATED:20240313T094824Z DTSTAMP:20240313T094824Z URL:https://ets24.nl/index.php/home/program/conference-program/industrial-session-2 DESCRIPTION:\N \N \N Moderator:\N \N Davide Apello\N \N\N\N \N \N Affiliation:\N \N Technoprobe (IT)\N \N\N\N \N \N The advances in Shift-left within DFT\N \N \N \N \N \N Author:\N \N Lee Harrison\N \N \N \N \N \N Affiliation:\N \N Siemens Digital Industries Software (UK)\N \N \N \N \N \N Biography:\N \N \N \N \N Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 20 years of industry experience with Siemens Tessent DFT products and has been involved in the specification of new test features and methodologies for Siemens customers, delivering high quality DFT solutions. With a focus on safety and security, Lee is working to ensure that current and future DFT requirements of Siemens’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.\N \N \N \N \N \N Ingredients to meet Market Demands for Alternative Test Solutions\N \N \N \N \N \N Author:\N \N Ric Dokken\N \N \N \N \N \N Affiliation:\N \N Roguevation (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N Automatic Test Equipment (ATE) dates back to 1960 when Teradyne was founded.  Additional companies including Fairchild Test Systems and Takeda Riken Industries (now Advantest) quickly followed.  In the 6+ decades since, ATE products have become enormously more capable and sophisticated.  Key drivers for test solutions today include the conflicting goals of test coverage and cost of test.  To meet test coverage goals, more products now require a system level test (SLT) step.  Adding a test step to a product must add cost, yet the cost economics of test are critical to the success and viability of a semiconductor product.  In some cases, these challenges demand alternatives to conventional ATE.  Some semiconductor product engineering groups have developed alternatives to conventional ATE with focused solutions.  Creating robust feature-rich solutions equal to commercial ATE products that have matured over decades has hurdles.  These hurdles can be overcome by use of test ingredients that are available today.  This paper explores how these ingredients can be used to create feature-rich cost-effective test solutions focused to specific requirements.\N \N \N \N \N \N Biography:\N \N \N \N \N Ric has led Roguevation since its inception in 2009, quickly guiding the company to profitability. He has provided the vision for unique and innovative semiconductor test software products that are deployed around the globe.  Prior to forming Roguevation, Ric was co-founder of the DFT-focused ATE company Inovys. As VP of Engineering, Ric was responsible for product development, and continued to lead engineering through the Verigy (Advantest) acquisition.  Ric began his career at Trillium (LTX) where he held positions in Support, Applications, and Marketing. Ric has a BSEET from DeVry Institute of Technology, Phoenix, AZ.\N \N \N \N \N \N DFT and Silicon Health Optimization with AI-Driven Test and Silicon Lifecycle Management\N \N \N \N \N \N Author:\N \N Yervant Zorian\N \N \N \N \N \N Affiliation:\N \N Synopsys (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N Increasing performance and reliability demands associated with today’s advanced technologies have created unprecedented challenges in both test and reliability analytics. With a growing engineering talent shortage, traditional manual approaches are no longer adequate for successful test and reliability deployment. Efficient silicon data analytics is also now essential to process the sheer volume of data needed to optimize the entire process from design to production to field. The application of Artificial Intelligence (AI) throughout the EDA stack is an innovative solution that provides increased test and reliability optimization and delivers results which are almost impossible to achieve manually. This presentation will introduce pioneering AI-driven solutions from Synopsys that are enabling DFX optimization, allowing users to achieve the best QoR and reduce time-to-market. The session will also explore the latest production analytics and multi-die silicon health management solutions from Synopsys’ Silicon Lifecycle Management (SLM), which provides silicon insights and operational metrics at every phase of the system lifecycle.\N \N \N \N \N \N Biography:\N \N \N \N \N Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. He is President of IEEE Test Technology Technical Council (TTTC), the Founder of IEEE 1500 Standardization Working Group, and General Chair of the 50th Design Automation Conference (DAC) and 50th International Test Conference (ITC). He authored 5 books, 400 referred papers, and holds 45 US patents. A Fellow of IEEE, Dr. Zorian has been the recipient of 2005 IEEE CAS Industrial Pioneer Award, 2006 IEEE Hans Karlsson Award, 2014 Republic of Armenia's National Medal of Science, and 2022 IEEE TTTC Lifetime Contribution Medal.\N \N \N \N \N \N Delivering Comprehensive Test Solutions for Today's Advanced Semiconductors\N \N \N \N \N \N Author:\N \N Steve Pruitt\N \N \N \N \N \N Affiliation:\N \N Teradyne (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N Semiconductors are becoming more and more complex, across all applications, driving the need for additional test. Learn how quality and cost of test can be optimized with Teradyne's comprehensive portfolio of test solutions that include ATE, SLT, and innovative tools that support advanced analytics and increased productivity.\N \N \N \N \N \N Biography:\N \N \N \N \N Stephen Pruitt is a seasoned marketing leader with a strong track record in the semiconductor industry, having held various technical, sales, marketing and management positions. As the Senior Director of SoC Business and Marketing Strategy at Teradyne, he plays a pivotal role in driving business revenue and profitability for the Semiconductor Test Division. Stephen's responsibilities include cross-functional division integration, business and market strategy development, and sales execution. Prior to Teradyne, Stephen served as Consulting Manager at Deloitte Consulting LLP, where he managed critical transformation initiatives for clients in the semiconductor sector. He holds a B.S. degree in electrical engineering from the University of Arizona and a M.B.A from Babson College.\N \N \N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderator: Davide Apello

Affiliation: Technoprobe (IT)

The advances in Shift-left within DFT

Author: Lee Harrison

Affiliation: Siemens Digital Industries Software (UK)

Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 20 years of industry experience with Siemens Tessent DFT products and has been involved in the specification of new test features and methodologies for Siemens customers, delivering high quality DFT solutions. With a focus on safety and security, Lee is working to ensure that current and future DFT requirements of Siemens’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.

Ingredients to meet Market Demands for Alternative Test Solutions

Author: Ric Dokken

Affiliation: Roguevation (US)

Automatic Test Equipment (ATE) dates back to 1960 when Teradyne was founded.  Additional companies including Fairchild Test Systems and Takeda Riken Industries (now Advantest) quickly followed.  In the 6+ decades since, ATE products have become enormously more capable and sophisticated.  Key drivers for test solutions today include the conflicting goals of test coverage and cost of test.  To meet test coverage goals, more products now require a system level test (SLT) step.  Adding a test step to a product must add cost, yet the cost economics of test are critical to the success and viability of a semiconductor product.  In some cases, these challenges demand alternatives to conventional ATE.  Some semiconductor product engineering groups have developed alternatives to conventional ATE with focused solutions.  Creating robust feature-rich solutions equal to commercial ATE products that have matured over decades has hurdles.  These hurdles can be overcome by use of test ingredients that are available today.  This paper explores how these ingredients can be used to create feature-rich cost-effective test solutions focused to specific requirements.

Ric has led Roguevation since its inception in 2009, quickly guiding the company to profitability. He has provided the vision for unique and innovative semiconductor test software products that are deployed around the globe.  Prior to forming Roguevation, Ric was co-founder of the DFT-focused ATE company Inovys. As VP of Engineering, Ric was responsible for product development, and continued to lead engineering through the Verigy (Advantest) acquisition.  Ric began his career at Trillium (LTX) where he held positions in Support, Applications, and Marketing. Ric has a BSEET from DeVry Institute of Technology, Phoenix, AZ.

DFT and Silicon Health Optimization with AI-Driven Test and Silicon Lifecycle Management

Author: Yervant Zorian

Affiliation: Synopsys (US)

Increasing performance and reliability demands associated with today’s advanced technologies have created unprecedented challenges in both test and reliability analytics. With a growing engineering talent shortage, traditional manual approaches are no longer adequate for successful test and reliability deployment. Efficient silicon data analytics is also now essential to process the sheer volume of data needed to optimize the entire process from design to production to field. The application of Artificial Intelligence (AI) throughout the EDA stack is an innovative solution that provides increased test and reliability optimization and delivers results which are almost impossible to achieve manually. This presentation will introduce pioneering AI-driven solutions from Synopsys that are enabling DFX optimization, allowing users to achieve the best QoR and reduce time-to-market. The session will also explore the latest production analytics and multi-die silicon health management solutions from Synopsys’ Silicon Lifecycle Management (SLM), which provides silicon insights and operational metrics at every phase of the system lifecycle.

Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. He is President of IEEE Test Technology Technical Council (TTTC), the Founder of IEEE 1500 Standardization Working Group, and General Chair of the 50th Design Automation Conference (DAC) and 50th International Test Conference (ITC). He authored 5 books, 400 referred papers, and holds 45 US patents. A Fellow of IEEE, Dr. Zorian has been the recipient of 2005 IEEE CAS Industrial Pioneer Award, 2006 IEEE Hans Karlsson Award, 2014 Republic of Armenia's National Medal of Science, and 2022 IEEE TTTC Lifetime Contribution Medal.

Delivering Comprehensive Test Solutions for Today's Advanced Semiconductors

Author: Steve Pruitt

Affiliation: Teradyne (US)

Semiconductors are becoming more and more complex, across all applications, driving the need for additional test. Learn how quality and cost of test can be optimized with Teradyne's comprehensive portfolio of test solutions that include ATE, SLT, and innovative tools that support advanced analytics and increased productivity.

Stephen Pruitt is a seasoned marketing leader with a strong track record in the semiconductor industry, having held various technical, sales, marketing and management positions. As the Senior Director of SoC Business and Marketing Strategy at Teradyne, he plays a pivotal role in driving business revenue and profitability for the Semiconductor Test Division. Stephen's responsibilities include cross-functional division integration, business and market strategy development, and sales execution. Prior to Teradyne, Stephen served as Consulting Manager at Deloitte Consulting LLP, where he managed critical transformation initiatives for clients in the semiconductor sector. He holds a B.S. degree in electrical engineering from the University of Arizona and a M.B.A from Babson College.

LAST-MODIFIED:20240521T122001Z SEQUENCE:5970697 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Van Gogh + Monet X-ACCESS:1 X-HITS:788 X-COLOR:88b3cd X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240522T110000 DTEND;TZID=Europe/Amsterdam:20240522T123000 UID:387A0DD7-936A-4D9F-9DB3-A2C5C144D6AC SUMMARY:Industrial Session 3 CREATED:20240313T094906Z DTSTAMP:20240313T094906Z URL:https://ets24.nl/index.php/home/program/conference-program/industrial-session-3 DESCRIPTION:\N \N \N Moderator:\N \N Alessia Galli\N \N\N\N \N \N Affiliation:\N \N Technoprobe (IT)\N \N\N\N \N \N Combining Built-In Redundancy Analysis with ECC for Memory Testing\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Luc Romain\N \N 1\N \N , Paul-Patrick Nordmann\N \N 2\N \N , Benoit Nadeau-Dostie\N \N 1\N \N , Lori Schramm\N \N 3\N \N , Martin Keim\N \N 3\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Siemens Digital Industries (CA),\N \N 2\N \N Siemens Digital Industries (DE),\N \N 3\N \N Siemens Digital Industries (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N Error Correction Codes (ECC) in current designs typically serve two purposes. For emerging non-volatile memory types (NVM), such as embedded magnetoresistive random access memory (eMRAM), ECC is necessary to counter the probabilistic behavior of the NVM, rendering the combined NVM/ECC a deterministic memory again. The second and much more prominent usage of ECC today is to protect the system against transient faults in the memory, here typically for SRAMs. On the other hand, new defect types for such emerging memories and new technology nodes may exceed reasonable costs of conventional row and column repair. To improve yield, users explore ECC as an option to augment the repair capability of the memory. This paper brings such an augmentation into a standard memory test and repair flow. It allows a user-defined, post silicon trade-off of using all or parts of the corrective power of the ECC for yield improvements and/or for system protection. Experimental results underline the very low area cost of this augmentation.\N \N \N \N \N \N Biography:\N \N \N \N \N Luc Romain is a Principal Software Development Engineer at Siemens where he develops design-for-test tools. He has been working in the EDA industry since 1999. He is based in Kanata, Canada. His main area of expertise is IC memory test, redundancy analysis and self-repair. Luc holds a bachelor and a master’s degree in Electrical Engineering from Ecole Polytechnique de Montreal.\N \N \N \N \N \N Semiconductor Application Fail Root Causes And Secure Test Remedy\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Heguo Yin\N \N 1\N \N , Peter Poechmueller\N \N 2\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Shandong University (CN),\N \N 2\N \N Neumonda GmbH (DE)\N \N \N \N \N \N Abstract:\N \N \N \N \N In this article we want to show root causes in semiconductor memory fails which occur despite extensive state of the art testing methodologies. Such fails typically occur in customer applications and when these fails are returned to the original semiconductor manufacturer for retest they are very hard to find or even undetectable. We investigate such fail mechanisms and postulate methods how to detect and remedy them during test as to restore trust into secure semiconductor performance. Finally, we show the implementation of a new test system which has been developed to prove concepts in practice.\N \N \N \N \N \N Biography:\N \N \N \N \N CEO of Neumonda, has dedicated his entire career to DRAM memory. First at Siemens where he held various roles in DRAM design and packaging, testing and manufacturing at German, Asian and U.S. locations. Then at Infineon and Qimonda, where he was head of all product development and backend plant manager. He has filed more than 100 memory-related patents. The insights he gained into customer application problems shaped his determination to find a new approach to DRAM testing.\N \N \N \N \N \N Power-Aware Test Scheduling for Memory BIST\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Albert Au\N \N 1\N \N , Michał Kępiński\N \N 2\N \N , Artur Pogiel\N \N 2\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Siemens Digital Industries (CA),\N \N 2\N \N Siemens Digital Industries (PL)\N \N \N \N \N \N Abstract:\N \N \N \N \N An increasing number of embedded memory instances, despite lowering the power supply voltage and technology node size, leads to higher power dissipation during the memory test phase when manufacturing a System-on-Chip (SoC). Commonly used manual memory test scheduling techniques need to be replaced with more systematic approaches. The objective is to minimize the test time through concurrent memory testing and, at the same time, maximize the dissipated power in the way the given power budget is not exceeded. The paper comprises two topics. First, it presents a toolchain aimed at a thorough monitoring of the power dispersed by memory instances and associated Memory Built-In Self-Test (MBIST) instruments. Secondly, several algorithms are proposed that optimize the memory test scheduling for a commercial Design-for-Test (DFT) tool.\N \N \N \N \N \N Biography:\N \N \N \N \N Artur Pogiel received the Ph.D. degree in electrical engineering from Poznań Univ. of Technology, Poland. In 2008 he joined Mentor Graphics. He is currently a Technical Engineering Manager for memory BIST tools at Siemens DISW. His main research interests include memory BIST, fault diagnosis, and embedded test. He co-authored 20+ technical papers and holds 8 US patents. Dr. Pogiel was the co-recipient of the Best Paper Awards at 2009 IEEE VLSI Design Conf. and 2011 IEEE European Test Symposium.\N \N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderator: Alessia Galli

Affiliation: Technoprobe (IT)

Combining Built-In Redundancy Analysis with ECC for Memory Testing

Authors: Luc Romain 1 , Paul-Patrick Nordmann 2 , Benoit Nadeau-Dostie 1 , Lori Schramm 3 , Martin Keim 3

Affiliations: 1 Siemens Digital Industries (CA), 2 Siemens Digital Industries (DE), 3 Siemens Digital Industries (US)

Error Correction Codes (ECC) in current designs typically serve two purposes. For emerging non-volatile memory types (NVM), such as embedded magnetoresistive random access memory (eMRAM), ECC is necessary to counter the probabilistic behavior of the NVM, rendering the combined NVM/ECC a deterministic memory again. The second and much more prominent usage of ECC today is to protect the system against transient faults in the memory, here typically for SRAMs. On the other hand, new defect types for such emerging memories and new technology nodes may exceed reasonable costs of conventional row and column repair. To improve yield, users explore ECC as an option to augment the repair capability of the memory. This paper brings such an augmentation into a standard memory test and repair flow. It allows a user-defined, post silicon trade-off of using all or parts of the corrective power of the ECC for yield improvements and/or for system protection. Experimental results underline the very low area cost of this augmentation.

Luc Romain is a Principal Software Development Engineer at Siemens where he develops design-for-test tools. He has been working in the EDA industry since 1999. He is based in Kanata, Canada. His main area of expertise is IC memory test, redundancy analysis and self-repair. Luc holds a bachelor and a master’s degree in Electrical Engineering from Ecole Polytechnique de Montreal.

Semiconductor Application Fail Root Causes And Secure Test Remedy

Authors: Heguo Yin 1 , Peter Poechmueller 2

Affiliations: 1 Shandong University (CN), 2 Neumonda GmbH (DE)

In this article we want to show root causes in semiconductor memory fails which occur despite extensive state of the art testing methodologies. Such fails typically occur in customer applications and when these fails are returned to the original semiconductor manufacturer for retest they are very hard to find or even undetectable. We investigate such fail mechanisms and postulate methods how to detect and remedy them during test as to restore trust into secure semiconductor performance. Finally, we show the implementation of a new test system which has been developed to prove concepts in practice.

CEO of Neumonda, has dedicated his entire career to DRAM memory. First at Siemens where he held various roles in DRAM design and packaging, testing and manufacturing at German, Asian and U.S. locations. Then at Infineon and Qimonda, where he was head of all product development and backend plant manager. He has filed more than 100 memory-related patents. The insights he gained into customer application problems shaped his determination to find a new approach to DRAM testing.

Power-Aware Test Scheduling for Memory BIST

Authors: Albert Au 1 , Michał Kępiński 2 , Artur Pogiel 2

Affiliations: 1 Siemens Digital Industries (CA), 2 Siemens Digital Industries (PL)

An increasing number of embedded memory instances, despite lowering the power supply voltage and technology node size, leads to higher power dissipation during the memory test phase when manufacturing a System-on-Chip (SoC). Commonly used manual memory test scheduling techniques need to be replaced with more systematic approaches. The objective is to minimize the test time through concurrent memory testing and, at the same time, maximize the dissipated power in the way the given power budget is not exceeded. The paper comprises two topics. First, it presents a toolchain aimed at a thorough monitoring of the power dispersed by memory instances and associated Memory Built-In Self-Test (MBIST) instruments. Secondly, several algorithms are proposed that optimize the memory test scheduling for a commercial Design-for-Test (DFT) tool.

Artur Pogiel received the Ph.D. degree in electrical engineering from Poznań Univ. of Technology, Poland. In 2008 he joined Mentor Graphics. He is currently a Technical Engineering Manager for memory BIST tools at Siemens DISW. His main research interests include memory BIST, fault diagnosis, and embedded test. He co-authored 20+ technical papers and holds 8 US patents. Dr. Pogiel was the co-recipient of the Best Paper Awards at 2009 IEEE VLSI Design Conf. and 2011 IEEE European Test Symposium.

LAST-MODIFIED:20240326T144452Z SEQUENCE:1140946 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Van Gogh + Monet X-ACCESS:1 X-HITS:691 X-COLOR:88b3cd X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240523T110000 DTEND;TZID=Europe/Amsterdam:20240523T123000 UID:CC961CF6-47B5-490B-80B2-EAAA650985EF SUMMARY:​​Industrial Session 4 CREATED:20240320T150101Z DTSTAMP:20240320T150101Z URL:https://ets24.nl/index.php/home/program/conference-program/industrial-session-6 DESCRIPTION:Panel on Testing Processors, high-end SoCs and Chiplets\NTitle: What will be required to effectively test processors, high end SoC or chiplet: will we need new DFT, a lot of silicon sensor data or applying more SLT?\NModerator: Matteo Sonza Reorda - Politecnico di Torino (IT)\NPanelists: Nir Sever - Proteantecs (IL), Ric Dokken - Roguevation (US), Adit Singh, Auburn University (US), Juergen Alt, Infineon (DE), Yervant Zorian, Synopsys (US)\NOrganizers: Davide Appello – VP Center of Excellence (Technoprobe – Cernusco L, Italia)\N \NAbstract\NAfter years of relentless introduction of innovative DFT technologies, it is less clear if there is a specific key enabler of a successful test strategy for high-power processors or chiplet. The industry is reacting to the continuous complexity increase with different approaches which are not necessarily designed to determine an efficient coexistence. However, there are different directions which apparently offer good motivations to be classified as must-have in the test strategy. The panelists are asked to debate and motivate if they foresee the test strategy of future chips driven by one specific DFT/test solution or by the ability to combine in a cost-efficient, industrially sustainable, and quality-effective mix of methods including DFT, SLM and SLT. X-ALT-DESC;FMTTYPE=text/html:

Panel on Testing Processors, high-end SoCs and Chiplets

Title: What will be required to effectively test processors, high end SoC or chiplet: will we need new DFT, a lot of silicon sensor data or applying more SLT?

Moderator: Matteo Sonza Reorda - Politecnico di Torino (IT)

Panelists: Nir Sever - Proteantecs (IL), Ric Dokken - Roguevation (US), Adit Singh, Auburn University (US), Juergen Alt, Infineon (DE), Yervant Zorian, Synopsys (US)

Organizers: Davide Appello – VP Center of Excellence (Technoprobe – Cernusco L, Italia)

 

Abstract

After years of relentless introduction of innovative DFT technologies, it is less clear if there is a specific key enabler of a successful test strategy for high-power processors or chiplet. The industry is reacting to the continuous complexity increase with different approaches which are not necessarily designed to determine an efficient coexistence. However, there are different directions which apparently offer good motivations to be classified as must-have in the test strategy. The panelists are asked to debate and motivate if they foresee the test strategy of future chips driven by one specific DFT/test solution or by the ability to combine in a cost-efficient, industrially sustainable, and quality-effective mix of methods including DFT, SLM and SLT.

LAST-MODIFIED:20240519T151314Z SEQUENCE:5184733 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:702 X-COLOR:88b3cd X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240523T140000 DTEND;TZID=Europe/Amsterdam:20240523T153000 UID:EEEEFBC0-4947-4F53-B172-62FAE802411A SUMMARY:Industrial Session 5 CREATED:20240313T094939Z DTSTAMP:20240313T094939Z URL:https://ets24.nl/index.php/home/program/conference-program/industrial-session-4 DESCRIPTION:\N Moderator: Nir Sever\N\N\N Affiliation: ProteanTecs (IL)\N\N\N\NHardware-Independent ATE Software for SLT\N \N\N\N Author: Ric Dokken\N\N\N Affiliation: Roguevation Inc. (US)\N\N Biography: \N\NRic has led Roguevation since its inception in 2009. He has provided the vision for unique and innovative semiconductor test software products that are deployed around the globe. Prior to forming Roguevation, Ric was co-founder of the DFT-focused ATE company Inovys and held the role of VP of Engineering. Ric began his career at Trillium (LTX) where he held positions in Support, Applications, and Marketing. Ric has a BSEET from DeVry Institute of Technology, Phoenix, AZ.\N\N\N\NIn-chip Monitoring for Extended Reliability Testing and Mission Profile Monitoring Feedback Loop\N \N\N\N Authors: Andrea Matteucci 1 , Luca Moriconi 2 \N\N\N Affiliations: 1 proteanTecs (IL), 2 ELES (IT)\N\N Abstract: \N\NThe reliability challenges of modern automotive and mission critical applications poses the risk that classical way of reliability testing, such as those outlined in industry standards like JEDEC JESD47 and JESD22, is insufficient. The mission profile at the base of existing standards were established decades ago and might not be representative of the requirements of modern mission-critical SoC, particularly those based on advanced FinFET nodes slated for deployment in the next generation of vehicles. To address this gap, innovative approaches are needed to guarantee the application of the adequate stress vs. mission profile, to measure performance degradation more precisely, and with fine granularity, simplifying the search for root cause analysis (RCA) and enabling an effective design for Zero Defects. This paper will explore the integration of advanced reliability test equipment, such as ELES ART5xx in combination with proteanTecs in-chip digital monitoring IP and analytics. Leveraging deep data extracted from in-chip monitors enables running more complex test sequences and checking their response on board during the oven stress time. The outcome is an efficient stress test capable of identifying and addressing design and process vulnerabilities.\N\N Biography: \N\NProduct manager and solution architect with 15+ years of professional experience in automotive development, from prototypes to mass production of powertrain applications, diagnostics, and ADAS/AD high-end scalable architecture. Andrea joined proteanTecs in 2020 to lead the design of automotive safety-compliant solutions. Before joining proteanTecs, Andrea served as the Chief Software Architect at Samsung Electronics, Product Owner at Zenuity, and Platform Project Manager at Bosch in Germany.\N\N\N\NVirtual Test Development Using Pre-Silicon Verification Environment\N \N\N\N Authors: E. Aderholz, Q. Atol, B. Baptist, W. Bharah, H. Holzner, R. Ignacio, V. Kamanuri, A. Kun, K. Ma, B. Mariacher, O. Pfabigan, A. Przybilla, D. Samardzic, F. Schlagbauer, M. Schleicher, J.P. Valiente, E. Vargas, K. Vinod, O. Zikulnig\N\N\N Affiliation: Infineon Technologies AG (DE)\N\N Abstract: \N\NThe demand for a fast time to market and competitive market entry in the semiconductor industry requires fast project execution. In an integrated circuit (IC) development project, the production test package development is very important and often one of the project’s critical paths to time-to-market. To cope with the project speed requirements and to deliver an effective production test solution, a new strategy and approach are needed. This paper describes the virtual test development (VTD) in Advantest V93k Automated Test Equipment (ATE). It uses the pre-silicon verification environment and the top-level IC design to simulate different production test cases, especially for the complex mixed-signal blocks. One of the objectives of the paper is to describe the process and relevant components for executing VTD. Using VTD, we can reduce the production test development cycle time by capturing early test program issues that otherwise can only be discovered during the real silicon trial using an ATE.\N\N Biography: \N\NPrincipal Engineer in Infineon's Automotive division focusing on test methodology. Worked as a technical lead in Infineon Austria, in collaboration with multidisciplinary teams across different Infineon sites, to complete the one of the pilot products that used Virtual Test Development methodology.\N\N\N\N X-ALT-DESC;FMTTYPE=text/html:

Moderator: Nir Sever

Affiliation: ProteanTecs (IL)

Hardware-Independent ATE Software for SLT

Author: Ric Dokken

Affiliation: Roguevation Inc. (US)

Ric has led Roguevation since its inception in 2009. He has provided the vision for unique and innovative semiconductor test software products that are deployed around the globe. Prior to forming Roguevation, Ric was co-founder of the DFT-focused ATE company Inovys and held the role of VP of Engineering. Ric began his career at Trillium (LTX) where he held positions in Support, Applications, and Marketing. Ric has a BSEET from DeVry Institute of Technology, Phoenix, AZ.

In-chip Monitoring for Extended Reliability Testing and Mission Profile Monitoring Feedback Loop

Authors: Andrea Matteucci 1 , Luca Moriconi 2

Affiliations: 1 proteanTecs (IL), 2 ELES (IT)

The reliability challenges of modern automotive and mission critical applications poses the risk that classical way of reliability testing, such as those outlined in industry standards like JEDEC JESD47 and JESD22, is insufficient. The mission profile at the base of existing standards were established decades ago and might not be representative of the requirements of modern mission-critical SoC, particularly those based on advanced FinFET nodes slated for deployment in the next generation of vehicles. To address this gap, innovative approaches are needed to guarantee the application of the adequate stress vs. mission profile, to measure performance degradation more precisely, and with fine granularity, simplifying the search for root cause analysis (RCA) and enabling an effective design for Zero Defects. This paper will explore the integration of advanced reliability test equipment, such as ELES ART5xx in combination with proteanTecs in-chip digital monitoring IP and analytics. Leveraging deep data extracted from in-chip monitors enables running more complex test sequences and checking their response on board during the oven stress time. The outcome is an efficient stress test capable of identifying and addressing design and process vulnerabilities.

Product manager and solution architect with 15+ years of professional experience in automotive development, from prototypes to mass production of powertrain applications, diagnostics, and ADAS/AD high-end scalable architecture. Andrea joined proteanTecs in 2020 to lead the design of automotive safety-compliant solutions. Before joining proteanTecs, Andrea served as the Chief Software Architect at Samsung Electronics, Product Owner at Zenuity, and Platform Project Manager at Bosch in Germany.

Virtual Test Development Using Pre-Silicon Verification Environment

Authors: E. Aderholz, Q. Atol, B. Baptist, W. Bharah, H. Holzner, R. Ignacio, V. Kamanuri, A. Kun, K. Ma, B. Mariacher, O. Pfabigan, A. Przybilla, D. Samardzic, F. Schlagbauer, M. Schleicher, J.P. Valiente, E. Vargas, K. Vinod, O. Zikulnig

Affiliation: Infineon Technologies AG (DE)

The demand for a fast time to market and competitive market entry in the semiconductor industry requires fast project execution. In an integrated circuit (IC) development project, the production test package development is very important and often one of the project’s critical paths to time-to-market. To cope with the project speed requirements and to deliver an effective production test solution, a new strategy and approach are needed. This paper describes the virtual test development (VTD) in Advantest V93k Automated Test Equipment (ATE). It uses the pre-silicon verification environment and the top-level IC design to simulate different production test cases, especially for the complex mixed-signal blocks. One of the objectives of the paper is to describe the process and relevant components for executing VTD. Using VTD, we can reduce the production test development cycle time by capturing early test program issues that otherwise can only be discovered during the real silicon trial using an ATE.

Principal Engineer in Infineon's Automotive division focusing on test methodology. Worked as a technical lead in Infineon Austria, in collaboration with multidisciplinary teams across different Infineon sites, to complete the one of the pilot products that used Virtual Test Development methodology.

LAST-MODIFIED:20240523T114011Z SEQUENCE:6141032 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Van Gogh + Monet X-ACCESS:1 X-HITS:637 X-COLOR:88b3cd X-SHOW-END-TIME:1 END:VEVENT END:VCALENDAR